The present invention relates to a semiconductor integrated circuit in which memories are integrated. Particularly, it relates to a semiconductor integrated circuit in which a logic circuit such as a CPU (central processing unit) is integrated with a large-capacity memory in one chip. For example, it relates to a useful technique adapted for embedded DRAM which is integrated with a CPU and a first level cache memory in one and the same chip.
Today, a semiconductor integrated circuit in which a large-scale logic circuit is integrated with a large-capacity memory in one chip is provided. In such a semiconductor integrated circuit, the number of bus bits for connecting the memory and the logic circuit to each other can be increased easily, for example, to 128 in order to enhance data throughput between the memory and the logic circuit. Accordingly, there is an advantage in that data can be transferred at a high speed while electric power consumption required for data input/output is suppressed compared with the case where input/output pins outside the chip are driven.
Multi-bank DRAM (Dynamic Random Access Memory) can be used as the large-capacity memory. In the multi-bank DRAM, a sense amplifier is provided in accordance with every memory bank, so that data once latched by the sense amplifier on the basis of a word line selecting operation can be output successively at a high speed by a simple means for changing over a column switch. Accordingly, data access to continuous addresses in one and the same page (one and the same word line address) can be made relatively speedily. Data access to different pages (at page-miss) is, however, made slow because of bit line precharge, or the like.
Further, in the multi-bank DRAM, page-miss can be hidden under a predetermined condition. That is, when a read or write command is generated to operate a certain memory bank and another memory bank is to be used next, an activation command can be given to the next memory bank in advance to make a word line selecting operation precedently. Of course, for this reason, the CPU must make access to the addresses sequentially. It is, however, substantially impossible to define this entirely by a CPU operation program, or the like.
In semiconductor integrated circuits, there is also that in which a cache memory integrated with a large-capacity memory and a large-scale logic circuit such as a CPU, or the like. In the semiconductor integrated circuit of this type, the difference in operating speed between the large-capacity memory and the CPU is relaxed by the cache memory so that data can be processed at a high speed by the CPU. That is, among data stored in the large-capacity memory, a part of data used recently by the CPU and data in its vicinity are held in the high-speed cache memory. The data processing speed is enhanced when the memory access of the CPU is hit to the cache memory. However, when a miss occurs once, access to the large-capacity memory is made. As a result, data processing speed of the CPU is limited.
An example of literature on the multi-bank DRAM is JP-A-10-65124 corresponding to U.S. patent application Ser. No. 08/813900 filed Mar. 7, 1997 and U.S. patent application Ser. No. 09/188367 filed Nov. 10, 1998, a continuation application of application Ser. No. 08/813900, the whole disclosure of which is incorporated herein by reference.
As described above, even in the multi-bank DRAM, page-miss is not always hidden in accordance with a sequence of access addresses. Even in the case where a cache memory is provided for the multi-bank DRAM, the situation is quite the same if cache-miss occurs. Therefore, the necessity of improving the access speed to the multi-bank memory more greatly has been found by the inventor.